A 32-Bit Signed/Unsigned Fixed Point Non-Restoring Square-Root Operation Using VHDL

After analyzing the advantages and disadvantages of all the general algorithms adopted in designing square root on FPGA chips with pipeline technology, a proposed algorithm based on digit by digit calculation method is discussed. The algorithm is realized on the ModelSim SE 6.3f development platform with VHDL language and the simulation results show that it is characterized by occupying less resource as well as processing is in a faster speed. Therefore it is an effective algorithm for implementing square root on commonly-used FPGA chips with pipeline technology. Square root operation deserves attention because of its frequent use in a number of applications. Square root operation basically is considered difficult to implement in hardware and it’s a basic operation in computer graphics and scientific calculation applications. A pipelined architecture to implement 32-bit fixed-point signed/unsigned square root operation on an FPGA using a non-restoring pipelined algorithm that does not require floating-point hardware is discussed. The main principle of proposed method is two-bit shifting and subtract-multiplexing operations, in order to achieve a simpler implementation and faster calculation. The proposed algorithm is used to implement FPGA based signed and unsigned 32-bit square root successfully and it is efficient in hardware resource. KeywordsPipelining, fixed-point arithmetic, signed and unsigned square root, non-restoring algorithm, FPGA, digit recurrence calculation.